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ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm ddr sdram unbuffered module 184pin unbuffered module based on 256mb e-die 64/72-bit ecc/non ecc revision 1.3 august. 2003 (ddr400 module)
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm revision history revision 1.0 (february, 2003) - first release revision 1.1 (february, 2003) - modified tac value +/-0.7ns => +/-0.65ns revision 1.2 (may, 2003) - corrected typo revision 1.3 (august, 2003) - corrected typo
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm samsung electronics co., ltd. reserves the right to change products and specif ications without notice. ordering information operating frequencies part number density organization component composition height m368l3223etm-c(l)cc/c4 256mb 32m x 64 32mx8( k4h560838e) * 8ea 1,250mil m368l6423etm-c(l)cc/c4 512mb 64m x 64 32mx8( k4h560838e) * 16ea 1,250mil m381l3223etm-c(l)cc/c4 256mb 32m x 72 32mx8( k4h560838e) * 9ea 1,250mil m381l6423etm-c(l)cc/c4 512mb 64m x 72 32mx8( k4h560838e) * 18ea 1,250mil cc(ddr400@cl=3) c4(ddr400@cl=3) speed @cl3 200mhz 200mhz cl-trcd-trp 3-3-3 3-4-4 feature ? power supply : vdd: 2.6v 0.1v, vddq: 2.6v 0.1v ? double-data-rate architecture; two data transfers per clock cycle ? bidirectional data strobe(dqs) ? differential clock inputs(ck and ck ) ? dll aligns dq and dqs transition with ck transition ? programmable read latency 3 (clock ) for ddr400 , 2.5 (clock) for ddr333 ? programmable burst length (2, 4, 8) ? programmable burst type (sequential & interleave) ? edge aligned data output, center aligned data input ? auto & self refresh, 7.8us re fresh interval(8k/64ms refresh) ? serial presence detect with eeprom ? pcb : height 1,250 (mil), single (256mb) and double(512mb) sided ? sstl_2 interface 184pin unbuffered dimm b ased on 256mb e-die (x8)
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm pin configuration (front side/back side) note : 1. * : these pins ar e not used in this module. 2. pins 44, 45, 47, 49, 51, 134, 135, 140, 142, 144 are used on x72 module, and are not used on x64 module. 3. pins 111, 158 are nc for 1 row module[m 368(81)l3223etm] & used for 2 row moduel[m368(81)l6423etm] pin front pin front pin front pin back pin back pin back 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 vref dq0 vss dq1 dqs0 dq2 vdd dq3 nc nc vss dq8 dq9 dqs1 vddq ck1 /ck1 vss dq10 dq11 cke0 vddq dq16 dq17 dqs2 vss a9 dq18 a7 vddq dq19 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 a5 dq24 vss dq25 dqs3 a4 vdd dq26 dq27 a2 vss a1 cb0 cb1 vdd dqs8 a0 cb2 vss cb3 ba1 dq32 vddq dq33 dqs4 dq34 vss ba0 dq35 dq40 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 vddq /we dq41 /cas vss dqs5 dq42 dq43 vdd */cs2 dq48 dq49 vss /ck2 ck2 vddq dqs6 dq50 dq51 vss vddid dq56 dq57 vdd dqs7 dq58 dq59 vss nc sda scl 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 vss dq4 dq5 vddq dm0 dq6 dq7 vss nc nc nc vddq dq12 dq13 dm1 vdd dq14 dq15 cke1 vddq *ba2 dq20 a12 vss dq21 a11 dm2 vdd dq22 a8 dq23 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 vss a6 dq28 dq29 vddq dm3 a3 dq30 vss dq31 cb4 cb5 vddq ck0 /ck0 vss dm8 a10 cb6 vddq cb7 vss dq36 dq37 vdd dm4 dq38 dq39 vss dq44 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 /ras dq45 vddq /cs0 /cs1 dm5 vss dq46 dq47 */cs3 vddq dq52 dq53 *a13 vdd dm6 dq54 dq55 vddq nc dq60 dq61 vss dm7 dq62 dq63 vddq sa0 sa1 sa2 vddspd key key pin description pin name function pin name function a0 ~ a12 address input (multiplexed) dm0 ~ 7, 8(for ecc) data - in mask ba0 ~ ba1 bank select address vdd power supply (2.6v) dq0 ~ dq63 data input/output vddq power supply for dqs(2.6v) dqs0 ~ dqs8 data strobe input/output vss ground ck0,ck0 ~ ck2, ck2 clock input vref power supply for reference cke0, cke1(for double banks) clock enable input vddspd se rial eeprom power/supply ( 2.3v to 3.6v ) cs0 , cs1 (for double banks) chip select input sda serial data i/o ras row address strobe scl serial clock cas column address strobe sa0 ~ 2 address in eeprom we write enable nc no connection cb0 ~ cb7 (for x72 module) check bit(data-in/data-out)
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm 256mb, 32m x 64 non ecc module (m368l3223etm) (populated as 1 bank of x8 ddr sdram module) functional block diagram a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7 cs 0 cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 2 dqs dqs dqs dqs v ss d0 - d7 d0 - d7 v dd /v ddq d0 - d7 d0 - d7 vref v ddspd spd notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% clock wiring ck0/ck0 clock input sdrams ck1/ck1 3 sdrams 3 sdrams 2 sdrams ck2/ck2 a0 - a12 a0-a12 : ddr sdrams d0 - d7 ras ras : ddr sdrams d0 - d7 cas cas : ddr sdrams d0 - d7 we we : ddr sdrams d0 - d7 cke0 cke : ddr sdrams d0 - d7 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d7 *clock net wiring card edge d3/d0/d6 cap/cap/cap d4/d1/d7 cap/cap/cap d5/d2/cap cap/cap/cap r=120 ? cap will replace dram *if two drams are loaded, ck0/1/2
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm 256mb, 32m x 72 ecc module (m381l3223etm) (populated as 1 bank of x8 ddr sdram module) functional block diagram a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 5.1 ohms + 5% clock wiring ck0/ck0 clock input sdrams ck1/ck1 3 sdrams 3 sdrams 3 sdrams ck2/ck2 dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0 i/o 5 i/o 4 i/o 3 i/o 2 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 i/o 5 i/o 4 i/o 3 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 i/o 5 i/o 4 i/o 3 i/o 2 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 i/o 5 i/o 4 i/o 3 i/o 2 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4 i/o 5 i/o 4 i/o 3 i/o 2 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 i/o 5 i/o 4 i/o 3 i/o 2 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 i/o 5 i/o 4 i/o 3 i/o 2 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 i/o 5 i/o 4 i/o 3 i/o 2 dm7 cs 0 cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs2 dqs dqs3 dqs dm6 dqs6 dqs7 dq15 i/o 2 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 7 i/o 6 i/o 1 i/o 0 d8 i/o 5 i/o 4 i/o 3 i/o 2 cs dqs8 dm8 dqs dqs dqs dqs dqs v ss d0 - d8 d0 - d8 v dd /v ddq d0 - d8 d0 - d8 vref v ddspd spd a0 - a12 a0-a12 : ddr sdrams d0 - d8 ras ras : ddr sdrams d0 - d8 cas cas : ddr sdrams d0 - d8 we we : ddr sdrams d0 - d8 cke0 cke : ddr sdrams d0 - d8 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d8 card edge d3/d0/d6 cap/cap/cap d4/d1/d7 cap/cap/cap d5/d2/d8 cap/cap/cap r=120 ? ck0/1/2
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0 dm d8 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 dm d9 i/o 5 i/o 4 i/o 3 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 dm d10 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 dm d11 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4 dm d12 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 dm d13 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 dm d14 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 dm d15 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm7 cs0 cs1 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6 dqs6 dqs7 dq15 i/o 2 i/o 5 dqs dqs dqs dqs dqs dqs dqs dqs dqs 512mb, 64m x 64 non ecc module (m368l6423etm) (populated as 2 bank of x8 ddr sdram module) functional block diagram clock wiring ck0/ck0 clock input sdrams ck1/ck1 4 sdrams 6 sdrams 6 sdrams ck2/ck2 a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d15 d0 - d15 v dd /v ddq d0 - d15 d0 - d15 vref v ddspd spd notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 3.0 ohms + 5% a0 - a12 a0-a12 : ddr sdrams d0 - d15 ras ras : ddr sdrams d0 - d15 cas cas : ddr sdrams d0 - d15 we we : ddr sdrams d0 - d15 cke1 cke : ddr sdrams d8 - d15 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d15 cke0 cke : ddr sdrams d0 - d7 *clock net wiring card edge d3/d0/d5 d4/d1/d6 cap/d2/d7 cap/d8/d13 d11/d9/d14 d12/d10/d15 r=120 ? ck0/1/2 cap will replace dram *if four drams are loaded, * *
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm 512mb, 64m x 72 ecc module (m381l6423etm) (populated as 2 bank of x8 ddr sdram module) functional block diagram dq4 dq5 dq6 dq7 dq0 dq1 dq2 dq3 dm i/o 7 i/o 6 i/o 1 i/o 0 d0 dm0 dm d9 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq12 dq13 dq14 dq8 dq9 dq10 dq11 dm i/o 7 i/o 6 i/o 1 i/o 0 d1 dm d10 i/o 5 i/o 4 i/o 3 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 dm1 dq20 dq21 dq22 dq23 dq16 dq17 dq18 dq19 dm i/o 7 i/o 6 i/o 1 i/o 0 d2 dm d11 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm2 dq28 dq29 dq30 dq31 dq24 dq25 dq26 dq27 dm i/o 7 i/o 6 i/o 1 i/o 0 d3 dm d12 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm3 dq36 dq37 dq38 dq39 dq32 dq33 dq34 dq35 dm i/o 7 i/o 6 i/o 1 i/o 0 d4 dm4 dm d13 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq44 dq45 dq46 dq47 dq40 dq41 dq42 dq43 dm i/o 7 i/o 6 i/o 1 i/o 0 d5 dm d14 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm5 dq52 dq53 dq54 dq55 dq48 dq49 dq50 dq51 dm i/o 7 i/o 6 i/o 1 i/o 0 d6 dm d15 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dq60 dq61 dq62 dq63 dq56 dq57 dq58 dq59 dm i/o 7 i/o 6 i/o 1 i/o 0 d7 dm d16 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 dm7 cs 0 cs1 cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs cs dqs0 dqs dqs4 dqs1 dqs5 dqs dqs dqs2 dqs dqs dqs3 dqs dqs dm6 dqs6 dqs7 dq15 i/o 2 i/o 5 cb4 cb5 cb6 cb7 cb0 cb1 cb2 cb3 dm i/o 7 i/o 6 i/o 1 i/o 0 d8 dm d17 i/o 5 i/o 4 i/o 3 i/o 2 i/o 0 i/o 1 i/o 6 i/o 7 i/o 2 i/o 3 i/o 4 i/o 5 cs cs dqs8 dm8 dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs dqs a0 serial pd a1 a2 sa0 sa1 sa2 scl sda wp v ss d0 - d17 d0 - d17 v dd /v ddq d0 - d17 d0 - d17 vref v ddspd spd * clock wiring ck0/ck0 clock input sdrams ck1/ck1 6 sdrams 6 sdrams 6 sdrams ck2/ck2 notes : 1. dq-to-i/o wiring is shown as recommended but may be changed. 2. dq/dqs/dm/cke/cs relationships must be maintained as shown. 3. dq, dqs, dm/dqs resistors: 22 ohms + 5%. 4. bax, ax, ras , cas , we resistors: 3.0 ohms + 5% a0 - a12 a0-a12 : ddr sdrams d0 - d17 ras ras : ddr sdrams d0 - d17 cas cas : ddr sdrams d0 - d17 we we : ddr sdrams d0 - d17 cke1 cke : ddr sdrams d9 - d17 ba0 - ba1 ba0-ba1 : ddr sdrams d0 - d17 cke0 cke : ddr sdrams d0 - d8 card edge d3/d0/d5 d4/d1/d6 d8/d2/d7 d17/d9/d14 d12/d10/d15 d13/d11/d16 r=120 ? ck0/1/2 *d8, d17 is assigned for ecc comp.
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in , v out -0.5 ~ 3.6 v voltage on v dd & v ddq supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.5 * # of component w short circuit current i os 50 ma note : permanent device damage may occur if abs olute maximum ratings are exceeded. functional operation should be restri cted to recommend operation condition. exposure to higher than recommended voltage for extended per iods of time could affect device reliability. dc operating conditions recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 70 c) parameter symbol min max unit note supply voltage(for device with a nominal v dd of 2.5v) v dd 2.5 2.7 v 5 i/o supply voltage v ddq 2.5 2.7 v 5 i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage(system) v tt v ref -0.04 v ref +0.04 v2 input logic high voltage v ih (dc) v ref +0.15 v ddq +0.3 v input logic low voltage v il (dc) -0.3 v ref -0.15 v input voltage level, ck and ck inputs v in (dc) -0.3 v ddq +0.3 v input differential voltage, ck and ck inputs v id (dc) 0.36 v ddq +0.6 v 3 v-i matching: pullup to pulldown current ratio vi(ratio) 0.71 1.4 - 4 input leakage current i i -2 2 ua output leakage current i oz -5 5 ua output high current(normal strengh driver) ;v out = v tt + 0.84v i oh -16.8 ma output high current(normal strengh driver) ;v out = v tt - 0.84v i ol 16.8 ma output high current(half strengh driver) ;v out = v tt + 0.45v i oh -9 ma output high current(half strengh driver) ;v out = v tt - 0.45v i ol 9ma 1.vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on vref ma y not exceed +/-2% of the dc value. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref 3. v id is the magnitude of the diff erence between the input level on ck and the input level on ck . 4. the ratio of the pullup current to the pulldown current is specified for the same temperat ure and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents t he maximum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not e xceed 1/7 for device drain to sour ce voltages from 0.1 to 1.0. 5. this is the dc voltage supplied at t he dram and is inclusive of all noise up to 20mhz. any noise above 20mhz at the dram generated from any source other than the dram itse lf may not exceed the dc vo ltage range of 2.6v +/-100mv. note :
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm ddr sdram idd spec table (v dd =2.7v, t = 10 c) * module idd was calculated on the basis of component idd and can be differently measured according to dq loading cap. symbol m368l3223etm m381l3223etm unit notes cc(ddr400@cl=3) c4(ddr400@cl=3) cc(ddr400@cl=3) c4(ddr400@cl=3) idd0 840 800 950 900 ma idd1 1040 1040 1170 1170 ma idd2p 35 35 40 40 ma idd2f 240 240 270 270 ma idd2q 200 200 230 230 ma idd3p 440 440 500 500 ma idd3n 600 600 680 680 ma idd4r 1480 1480 1670 1670 ma idd4w 1520 1520 1710 1710 ma idd5 1440 1440 1620 1620 ma idd6 normal 24 24 27 27 ma low power 12 12 14 14 ma optional idd7a 2480 2320 2790 2610 ma (v dd =2.7v, t = 10 c) symbol m368l6423etm m381l6423etm unit notes cc(ddr400@cl=3) c4(ddr400@cl=3) cc(ddr400@cl=3) c4(ddr400@cl=3) idd0 1440 1400 1620 1580 ma idd1 1640 1640 1850 1850 ma idd2p65657575ma idd2f 480 480 540 540 ma idd2q 400 400 450 450 ma idd3p 880 880 990 990 ma idd3n 1200 1200 1350 1350 ma idd4r 2080 2080 2340 2340 ma idd4w 2120 2120 2390 2390 ma idd5 2040 2040 2300 2300 ma idd6 normal 48 48 54 54 ma low power 24 24 27 27 ma optional idd7a 3080 2920 3470 3290 ma
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm note : 1. vid is the magnitude of t he difference between the input level on ck and the input on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track va riations in the dc level of the same. 3. these parameters should be tested at the pim on actual components and may be c hecked at either the pin or the pad in simulation. the ac and dc input specif icatims are refation to a vref envelo pe that has been bandwidth limited 20mhz. output load circuit (sstl_2) output z0=50 ? c load =30pf v ref =0.5*v ddq r t =50 ? v tt =0.5*v ddq ac operating conditions parameter/condition symbol min max unit note input high (logic 1) voltage, dq, dq s and dm signals vih(ac) vref + 0.31 v input low (logic 0) voltage, dq, dqs and dm signals. vil(ac) vref - 0.31 v input differential voltage, ck and ck inputs vid(ac) 0.7 vddq+0.6 v 1 input crossing point voltage, ck and ck inputs vix(ac) 0.5*vddq-0.2 0.5*vddq+0.2 v 2 input/output capacitance (vdd=2.6v, vddq=2.6v, ta= 25 c, f=1mhz) parameter symbol m368l3223etm m381l3223etm unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin149575160pf input capacitance(cke0) cin2 42 50 44 53 pf input capacitance( cs 0) cin3 42 50 44 53 pf input capacitance( clk0, clk1,clk2) cin4 25 30 25 30 pf input capacitance(dm0~dm7, dm8(for ecc)) cin5 6767pf data & dqs input/output c apacitance(dq0~dq63) cout1 6767pf data input/output capacitance (cb0~cb7) cout2 - - 6 7 pf parameter symbol m368l6423etm m381l6423etm unit min max min max input capacitance(a0 ~ a12, ba0 ~ ba1,ras ,cas ,we )cin165816987pf input capacitance(cke0,cke1) cin2 42 50 44 53 pf input capacitance( cs 0, cs 1) cin3 42 50 44 53 pf input capacitance( clk0, clk1,clk2) cin4 28 34 28 34 pf input capacitance(dm0~dm7, dm8(for ecc)) cin5 10 12 10 12 pf data & dqs input/output capaci tance(dq0~dq63) cout1 10 12 10 12 pf data input/output capacitance (cb0~cb7) cout2 - - 10 12 pf
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm ac timing parameters and specifications parameter symbol cc(ddr400@cl=3) c4(ddr400@cl=3) unit note min max min max row cycle time trc 55 60 ns refresh row cycle time trfc 70 70 ns row active time tras 40 70k 40 70k ns ras to cas delay trcd 15 18 ns row precharge time trp 15 18 ns row active to row active delay trrd 10 10 ns write recovery time twr 15 15 ns internal write to read command delay twtr 2 2 tck clock cycle time cl=3.0 tck 510510ns 16 cl=2.5 612612ns clock high level width t ch 0.45 0.55 0.45 0.55 tck clock low level width tcl 0.45 0.55 0.45 0.55 tck dqs-out access time from ck/ck tdqsck -0.55 +0.55 -0.55 +0.55 ns output data access time from ck/ck tac -0.65 +0.65 -0.65 +0.65 ns data strobe edge to ouput data edge tdqsq - 0.4 - 0.4 ns 13 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.72 1.28 0.72 1.28 tck write preamble setup time twpres 0 0 ps 5 write preamble twpre 0.25 0.25 tck write postamble twpst 0.4 0.6 0.4 0.6 tck 4 dqs falling edge to ck rising-setup time tdss 0.2 0.2 tck dqs falling edge from ck rising-hold time tdsh 0.2 0.2 tck dqs-in high level width tdqsh 0.35 0.35 tck dqs-in low level width tdqsl 0.35 0.35 tck address and control input setup time tis 0.6 0.6 ns h,7~10 address and control input hold time tih 0.6 0.6 ns h,7~10 data-out high impedence time from ck/ck thz - tac max - tac max ns 3 data-out low impedence time from ck/ck tlz tac min tac max tac min tac max ns 3 mode register set cycle time tmrd 2 2 tck dq & dm setup time to dqs, slew rate 0.5v/ns tds 0.4 0.4 ns i, j dq & dm hold time to dqs, slew rate 0.5v/ns tdh 0.4 0.4 ns i, j dq & dm input pulse width tdipw 1.75 1.75 ns 9 control & address input pulse width for each input tipw 2.2 2.2 ns 9 refresh interval time up to 128mb trefi 15.6 15.6 us 6 256mb, 512mb, 1gb 7.8 7.8 us output dqs valid window tqh thp -tqhs - thp -tqhs -ns12 clock half period thp min tch/tcl - min tch/tcl - ns 11, 12
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm component notes 1.v id is the magnitude of the diff erence between the input level on ck and the input level on ck . 2. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 3. thz and tlz transitions occur in the same access time wi ndows as valid data transitions. t hese parameters are not referenc ed to a specific voltage level but s pecify when the device output in no longer driving (hz), or begins driving (lz). 4. the maximum limit for this paramete r is not a device limit. the device will operate with a greater value for this paramete r, but sys tem performance (bus turnaround) will degrade accordingly. 5. the specific requirement is that dqs be valid (high, low, or at some poi nt on a valid transition) on or before this ck edg e. a valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes we re previ ously in progress on the bus, dqs will be tran sitioning from high- z to logic low. if a pr evious write was in progress , dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 6. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 7. for command/address input slew rate 0.5 v/ns 8. for ck & ck slew rate 0.5 v/ns 9. these parameters guarantee device timing, but they are not necessarily tested on each device. they may be guaranteed by device design or tester correlation. 10. slew rate is measured between voh(ac) and vol(ac). 11. min (tcl, tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the mini mum specification limits for tcl and tch).....for example, tcl and tch are = 50% of th e period, less the half period jit ter (tjit(hp)) of the clock source, and less the half period jitter due to crosstalk (tji t(crosstalk)) into the clock traces. 12. tqh = thp - tqhs, where: thp = minimum half clock period for any given cycle and is defined by clock high or cloc k low (tch, tcl). tqhs accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of dqs on one tansition followed by the worst case pull-in of dq on the next transition, both of which are, separately, due to data pin skew and output pattern effec ts, and p- channel to n-channel variation of the output drivers. 13. tdqsq consists of data pin skew and output pattern effects, and p-channel to n-channel variati on of the output drivers for any given cycle. 14. tdal = (twr/tck) + (trp/tck) for each of the terms above, if not already an integer, round to the next highest integer. example: for ddr400(cc) at cl= 3 and tck=5ns tdal = (15 ns / 5 ns) + (15 ns/ 5ns) = (3) + (3) tdal = 6 clocks 15. in all circumstances, txsnr can be satisfied using t xsnr=trfcmin+1*tck 16. the only time that the cl ock frequency is allowed to change is during self-refresh mode. parameter symbol cc(ddr400@cl=3) c4(ddr400@cl=3) unit note min max min max data hold skew factor tqhs 0.5 0.5 ns 12 auto precharge write recovery + precharge time tdal - - - - ns 14 exit self refresh to non- read command txsnr 75 75 ns 15 exit self refresh to r ead command txsrd 200 - 200 - tck
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm table 4 : input/output setup & hold derating for rise/fall delta slew rate table 5 : output slew rate characteristice (x8 devices only) table 6 : output slew rate ch aracteristice (x16 devices only) table 7 : output slew rate matching ratio characteristics delta slew rate tds tdh units notes +/- 0.0 v/ns 0 0 ps i +/- 0.25 v/ns +50 +50 ps i +/- 0.5 v/ns +100 +100 ps i slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 1.0 4.5 a,c,d,f,g pulldown slew 1.2 ~ 2.5 1.0 4.5 b,c,d,f,g slew rate characteristic typical range (v/ns) minimum (v/ns) maximum (v/ns) notes pullup slew rate 1.2 ~ 2.5 0.7 5.0 a,c,d,f,g pulldown slew 1.2 ~ 2.5 0.7 5.0 b,c,d,f,g ac characteristics ddr400 parameter min max notes output slew rate matching ratio (pullup to pulldown) - - e,k system characteristics for ddr sdram the following specificat ion parameters are required in systems using ddr400 devices to ensure proper system perfor- mance. these characteristics are for system simu lation purposes and are guaranteed by design. table 1 : input slew rate for dq, dqs, and dm table 2 : input setup & hold time derating for slew rate table 3 : input/output setup & ho ld time derating for slew rate ac characteristics ddr400 parameter symbol min max units notes dq/dm/dqs input slew rate measured between vih(dc), vil(dc) and vil(dc), vih(dc) dcslew 0.5 4.0 v/ns a, k input slew rate tis tih units notes 0.5 v/ns 0 0 ps h 0.4 v/ns +50 0 ps h 0.3 v/ns +100 0 ps h input slew rate tds tdh units notes 0.5 v/ns 0 0 ps j 0.4 v/ns +75 +75 ps j 0.3 v/ns +150 +150 ps j
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm system notes : a. pullup slew rate is characteristized under the test conditions as shown in figure 1. output test point vssq 50 ? figure 1 : pullup slew rate test load b. pulldown slew rate is measured under the test conditions shown in figure 2. output test point vddq 50 ? figure 2 : pulldown slew rate test load c. pullup slew rate is measured between (vddq/2 - 320 mv +/- 250 mv) pulldown slew rate is measured between (vddq/2 + 320 mv +/- 250 mv) pullup and pulldown slew rate conditions are to be met fo r any pattern of data, including all outputs switching and only on e output switching. example : for typical slew rate, dq0 is switching for minmum slew rate, all dq bits are switching from either high to low, or low to high. for maximum slew rate, only one dq is switching from either high to low, or low to high. the remaining dq bits re main the same as for previous state. d. evaluation conditions typical : 25 c (t ambient), vddq = 2.6v, typical process minimum : 70 c (t ambient), vddq = 2.5v, slow - slow process maximum : 0 c (t ambient), vddq = 2.7v, fast - fast process e. the ratio of pullup slew rate to pulld own slew rate is specified for the same temperature and voltage, over the entire tempe rature and voltage range. for a given output, it represents the maxi mum difference between pullup and pulldown drivers due to process variation. f. verified under typical conditions for qualification purposes. g. tsopii package divices only. h. a derating factor will be used to in crease tis and tih in the case where t he input slew rate is below 0.5v/ns as shown in table 2. the input slew rate is based on the lesser of the slew rates det emined by either vih(ac) to vil(ac) or vih(dc) to vil(dc), similarly for rising transitions. i. a derating factor will be used to increase tds and tdh in the case where dq, dm, and dqs slew rates differ, as shown in tabl es 3 & 4. input slew rate is based on the larger of ac-ac delta rise , fall rate and dc-dc delta rise, input slew rate is based on the lesser of the slew rates determined by either vi h(ac) to vil(ac) or vih(dc) to vil( dc), similarly for rising transitions. the delta rise/fall rate is calculated as: {1/(slew rate1)} - {1/(slew rate2)} for example : if slew rate 1 is 0.5 v/ ns and slew rate 2 is 0.4 v/ns, then the delta rise, fall rate is - 0.5ns/v . using the table given, this would result in the need for an increase in tds and tdh of 100 ps.
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm j. table 3 is used to increase tds and tdh in the case where the i/o slew rate is below 0.5 v/ns . the i/o slew rate is based on the lesser on the lesser of the ac - ac slew ra te and the dc- dc slew rate. t he inut slew rate is based on the lesser of the slew rate s deter mined by either vih(ac) to vil(ac) or vih( dc) to vil(dc), and similarly for rising transitions. k. dqs, dm, and dq input slew rate is specified to prevent double clocking of data and preserve setup and hold times. signal tr ansi tions through the dc region must be monotony.
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm command truth table (v=valid, x=don t care, h=logic high, l=logic low) command cken-1 cken cs ras cas we ba0,1 a10/ap a0 ~ a9 a11, a12 note register extended mrs h x l l l l op code 1, 2 register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address (a0~a9, a11, a12) read & column address auto precharge disable hxlhlhv l column address 4 auto precharge enable h 4 write & column address auto precharge disable hxlhllv l column address 4 auto precharge enable h 4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks x h 5 active power down entry h l hx x x x lv vv exit l h x x x x precharge power down mode entry h l hx x x x lh hh exit l h hx x x lv vv dm h x x 8 no operation (nop) : not defined h x hx x x x 9 lh hh 9 note : 1. op code : operand code. a 0 ~ a 12 & ba 0 ~ ba 1 : program keys. (@emrs/mrs) 2. emrs/ mrs can be issued only at all banks precharge state. a new command can be issued 2 clock cycles after emrs or mrs. 3. auto refresh functi ons are same as the cbr refresh of dram. the automatical prechar ge without row precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. 4. ba 0 ~ ba 1 : bank select addresses. if both ba 0 and ba 1 are "low" at read, write, row acti ve and precharge, bank a is selected. if ba 0 is "high" and ba 1 is "low" at read, write, row acti ve and precharge, bank b is selected. if ba 0 is "low" and ba 1 is "high" at read, write, row ac tive and precharge, bank c is selected. if both ba 0 and ba 1 are "high" at read, write, row ac tive and precharge, bank d is selected. 5. if a 10 /ap is "high" at row precharge, ba 0 and ba 1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/writ e command can not be issued. another bank read/wr ite command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop co mmand is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges (write dm latency i s 0). 9. this combination is not defined for any function, which means "no o peration(nop)" in ddr sdram.
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm tolerances : 0.005(.13) unless otherwise specified. the used device is 32mx8 ddr sdram, tsopii. ddr sdram part no : k4h560838e. package dimensions 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.100 min (2.30 min) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.15 ) 0.250 (6.350) detail a 0.157 (4.00) 0.071 (1.80) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 2.500 0.7 0.10 m c ba 0.10 mc b a m 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 1.25 0.006 (31.75 0.15) (4.00) (2x) 0.157 (3.00) 0.118 0.07 max 0.050 0.0039 (1.270 0.10) (1.20 max) physical dimensions : 32m x 64 (m368l3223etm), 32m x 72 (m381l3223etm) n/a (for x64) ecc (for x72) n/a (for x64) ecc (for x72)
ddr sdram rev. 1.3 august. 2003 256mb, 512mb unbuffered dimm tolerances : 0.005(.13) unless otherwise specified. the used device is 32mx8 ddr sdram, tsopii. ddr sdram part no : k4h560838e package dimensions 5.25 0.006 5.077 units : inches (millimeters) 0.050 0.0078 0.006 (0.20 0.15) 0.145 max 0.050 0.0039 (1.270 0.10) 0.100 min (2.30 min) 0.393 (10.00) (1.270) 0.100 (2.50 ) detail b a b (128.950) (133.350 0.15 ) 0.250 (6.350) detail a 0.157 (4.00) 0.071 (1.80) (3.67 max) 0.039 0.002 (1.000 0.050) (3.80) 2.175 (6.62) (64.77) (49.53) (17.80) 2.55 1.95 0.26 2.500 0.7 0.10 m c ba 0.10 mc b a m 0.1496 (3.00) 0.118 r (2.00) 0.0787 (4.00) 0.1575 1.25 0.006 (31.75 0.15) (4.00) (2x) 0.157 (3.00) 0.118 physical dimensions : 64m x 64 (m368l6423etm), 64m x 72 (m381l6423etm) n/a (for x64) ecc (for x72) n/a (for x64) ecc (for x72)

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